1. Field of Invention
The present invention relates to integrated circuit design and in particular the modeling and timing verification of chip designs.
2. Description of Related Art
In high density integrated circuit design voltage drop caused by missing vias or an inadequate power network design can cause timing problems. In current design technology, voltage drop violations are flagged with respect to a predefined limit. No timing delay data is included in cell level timing verification, and chip design simulations with voltage drops are not based on cell timing models. In addition the simulation time is quite lengthy.
In U.S. Pat. No. 6,088,523 (Nabors et al.) a method and apparatus is directed for simulating an electrical circuit design using approximate circuit element tapers. In U.S. Pat. No. 5,949,689 (Olson et al.) is directed to a method and system for modeling power consumed by a logic cell in a computer controlled power estimation process. In U.S. Pat. No. 5,930,148 (Bjorksten et aL) a method and system for verifying is directed a digital circuit design including dynamic circuit cells that utilize diverse circuit techniques. In U.S. Pat. No. 5,878,053 (Koh et al.) hierarchical power network simulation and analysis tool is directed toward reliability testing of deep sub micron IC designs. However, the simulation and analysis does not include timing delay data. In U.S. Pat. No. 5,872,952 (Taun et al.) a method is directed toward power net analysis of integrated circuits. A power net simulator uses current values to calculate characteristics of the power network. In U.S. Pat. No. 5,598,348 a method and apparatus is directed to analyzing the power network of a VLSI circuit, but does not calculate cell timing delay data. In U.S. Pat. No. 5,471,409 (Tani) a logic and circuit simulation apparatus is directed to simulation based on signal propagation delay time and high reliability. However, the simulation does not use a voltage drop cell timing model. In U.S. Pat. No. 5,446,676 (Huang et al.) a method is directed to transistor level timing, power simulator and power analyzer.
In xe2x80x9cInterconnection Analysis for Standard Cell Layoutsxe2x80x9d Pedram et al., IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Vol. 18, No. Oct. 10, 1999, IEEE, pp1512-1519, a model and procedure is directed to predicting common physical design characteristics of standard cell layout, such as connection length and chip area. The predicted results are obtained from analysis of a net list and no finctionality of the design is used. In xe2x80x9cClock Skew Verification in the Presence of IR Drop in the Power Distribution Networkxe2x80x9d, Saleh et al., IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Vol. 19, No. Jun. 6, 2000, IEEE, pp635-644, methodology is presented directed to verification of clock delay and skew. An iterative technique is presented for clock simulation in the presence of full chip dynamic IR drop.
Current methods of verifying voltage drop generally identify voltage drop violations with respect to a predefined limit. No timing delay data is used for cell level timing verification. Chip design simulations, which include voltage drops, are not based on cell level timing model, and the simulation time is very long. Previous solutions set a global voltage drop limit which does not have a tight relationship with chip failures including timing failures. Whole chip circuit simulation requires a lot of simulation time and is affordable with few test vectors. A method is needed for cell level modeling and timing verification of chip designs with voltage drops being considered that can be accomplished in a reasonable amount of time.
It is an objective of the present invention to characterize cell timing variation rate with respect to voltage drops.
It is also an objective of the present invention to calculate incremental cell I/O (input/output) path delay in the presence of voltage drops.
It is further an objective of the present invention to perform whole chip, cell level timing verification.
It is still further an objective of the present invention to enable a fast, whole chip, cell level timing verification in the presence of voltage drops.
The present invention characterizes cell timing variation rate with respect to voltage drop for each cell in the design library. The incremental I/O path delay in the presence of voltage drops is calculated by adding delay changes to a nominal cell delay value. This is done for each power pin using voltage change values and timing variation rate caused by the power pin. Then a whole chip cell level timing data file is produced without considering voltage drops and is modified with a whole chip timing data file which includes voltage drops. The modified whole chip timing data file is used with traditional timing verification tools to perform a whole chip cell level timing verification which includes the effects of voltage drops.